The disclosed invention relates to large-scale integrated (LSI) and very large-scale integrated (VLSI) circuit structures, and is particularly directed to a logic design structure which includes shift register circuitry that allows testing of the AC characteristics of LSI and VLSI circuitry which incorporates the logic design structure of the invention.
The substantial advances in integrated circuit technology has resulted in LSI and VLSI circuit structures wherein literally hundreds of logic elements are placed on a single silicon chip. However, such high levels of integration present substantial problems in debugging and testing of LSI and VLSI circuits. Such problems are particularly acute with VLSI circuits. Simply stated, due to the nature of LSI and VLSI circuitry, internal nodes cannot be directed accessed and therefore specific internal circuitry cannot be directly tested. Such circuits can only be tested by transmitting and receiving signals through the external input/output (I/O) terminals of the circuits.
In the past, LSI circuits were tested by applying predetermined signals to input terminals and observing the signals at the output terminals. Realistically, such testing merely ascertained whether or not an LSI circuit accomplished certain results in response to the predetermined inputs. The performance of the individual circuitry within the LSI circuit could not be isolated, nor could faults be identified as being caused by specific circuitry.
The need for testability of LSI circuitry has led to the development of LSI design structures which allow limited types of testing and which provide desired insensitivity to AC characteristics such as clock signal rise and fall times and circuit delays.
Such LSI design structures include the use of set/scan registers wherein all internal storage elements (e.g., latches) are configured so that they can be selectively controlled to operate as shift registers for test purposes. For testing, predetermined input shift registers are configured to provide inputs to a combinational logic network, and predetermined output shift registers are configured to accept and store outputs from the combinational logic network. Test values are serially loaded into the predetermined input shift registers. After the prdetermined input shift registers contain the desired values, the contents of the predetermined output shift registers are observed by serially outputting the contents of the predetermined output registers.
A further development of set/scan registers is set forth in a paper entitled "A Logic Design Structure for LSI Testability," E. B. Eichelberger, et al., Proc. 14th Design Automation Conf., New Orleans, June 20-22, 1977, pp. 462-468. That paper sets forth a design for polarity-hold latches which are asserted to be hazard-free. When two of such latches are incorporated in a shift register latch, the latches of the shift register latch are clocked by non-overlapping clocks. The paper further provides design rules by which the latches disclosed therein are configured for the capability of operating as shift registers in order to simplify testing.
While substantial efforts have been directed to facilitating the testability of LSI circuits, presently known techniques such as those discussed above allow only DC testing of combinational logic whereby such combinational logic is tested only after predetermined values are serially loaded into the predetermined input shift register. Thus, for a given flip-flop in a predetermined input shift register, the value it receives could easily have been the same value that is currently stored in such flip-flop. If this occurs, the combinational logic network fed by such flip-flop will already have been stimulated to the desired test state. As a result, the combinational logic network would not be tested for its capability of being stimulated to the test value of the particular flip-flop.
It is generally accepted that with LSI technology detailed AC testing of combinational logic networks, also known as delay testing, is not possible. See, for example, the above referenced Eichelberger paper at page 466. See also, "Delay Testing LSI Logic," J. J. Shedletsky, Proc. 8th Annual International Conference On Fault Tolerant Computing, 1978, pp. 159-164. Moreover, to the extent AC test capability would be designed into the LSI design structure, it is generally recognized that all shift register latches would have to be capable of storing two values. Providing such capability with known design techniques would result in substantial additional complexity and substantially increased chip area overhead that would have to be devoted to test capability. As a result, the number of functions provided per unit chip area would be reduced.
Although the foregoing discussion generally references LSI circuitry, it also applies to VLSI circuitry with respect to which the lack of AC test capabilities is particularly important.